The present invention relates to a NAND cell type nonvolatile semiconductor memory device using an electrically erasable memory cell with a floating gate electrode for accumulation of electric charge layered beneath a control gate electrode. More particularly, the memory cell includes plural memory cells connected in series. The invention also relates to a data writing control method in such a memory device.
Nonvolatile semiconductor memory devices are known that can be electrically erased and integrated to a high degree such as an EEPROM (electrically erasable programmable ROM). Specifically, a NAND cell type EEPROM connecting a plurality of memory cells in series is known as providing a high degree of integration. In such a NAND cell type EEPROM, the memory cell has a "stacked gate structure" in which a control gate electrode is laminated on a floating gate electrode over an insulation film on a semiconductor substrate. A plurality of memory cells are connected in series so that cells share sources and drains with adjacent cells. The string of series connected cells make up one unit connected to the bit line to constitute the NAND cell. The NAND cells are arranged in a matrix to make up the memory cell device.
The NAND cells are arranged along the column direction of the memory cell array and the drain of the end cell is connected to the bit line, which is the data line, through each selection gate electrode. The other end of the string of NAND cells is connected to the source line through the selection gate electrode and further to the common source line, which also provides the reference potential. The control gate electrode and selection gate electrode of each memory cell are connected in common along the row direction of the memory cell array,with the control gate electrodes connected to the word lines, and the selection gate electrodes connected to the selection gate lines.
When writing such a NAND cell type EEPROM, if a lower voltage operation can be achieved, the transistors that make up the column decode circuitry connected to the bit lines can be chosen to be V.sub.CC transistors. Conseqeuntly, the area of the peripheral circuit can be reduced. To achieve such a lower voltage operation, various technologies have proposed and adopted a "self-boost writing system," thereby reducing the chip size. The operation of such a self-boost writing system is described below.
FIG. 19 is a diagram showing an equivalent circuit of a memory cell of this NAND cell type EEPROM. In the diagram, the symbol BL is a bit line, SG is a selection gate line, CG is a word line, and SL is a source line.
In the usual batch writing of plural pieces of data into plural memory cells along a row direction, writing starts from a memory cell at a position remote from the bit line BL.
In a random writing operation, arbitrary memory cells between bit line BL and source line SL are written randomly. When writing, 0V is first applied to the bit lines BL1 to BLn of the NAND cell connected to the memory cell into which "0" data is to be written. Consequently, in the bit lines BL1 to BLn of the NAND cell to which the memory cell to be written with "1" data is connected, the same voltage as the drain side selection gate voltage, a higher voltage, or a potential for sufficiently cutting off the drain side selection gate if lower than the drain side selection gate voltage is applied, so that write selection and non-selection (write disable) can be distinguished in the bit lines BL1 to BLn.
In this state, when a potential for turning on the memory cell, that is, a write pulse voltage V.sub.pp or a transfer voltage pulse V.sub.pass of non-selection word line, is applied to all word lines CG1 to CGn of the selection block, if a potential for turning on the memory cell is applied at a specified potential in the rise potential of the voltage pulse, OV is transferred to the channel of the NAND connected to the bit linesBL1 to BL2 for writing "0" data. Thus, when the write voltage pulse V.sub.pp is applied to the selection word lines CG1 to CGn connected to the memory cell to be written with "0" data, "0" data is written into the selection memory cell connected to the selection bit lines BL1to BLn to which 0V has been applied.
In the channel of the NAND cells connected to the bit lines BL1 to BLn to be written with "1" data, a specified initial potential, subtracting the threshold portion of the corresponding selection gate transistor from the potential of the bit lines BL1 to BLn through the selection gate line SG1 of the bit line side, is transferred from the bit lines BL1 to BLn. The bit line side selection gate transistor is cut off and floats. At this time, in the source line SL, 0V or a specified positive potential is applied in order to cut off sufficiently the source side selection gate.
Here, the channel potential of the non-selection memory cell connected to the selection word line to which write voltage pulse V.sub.pp is applied, for writing in "1" data, that is, the memory cell cutting off the bit line side selection gate transistor, with the channel in the floating state, must be sufficiently large so that "0" may not be written in. That is, the threshold fluctuation of the non-selection memory cell should be within an allowable range. This is because, in this memory cell, the fluctuation of threshold is smaller when the difference of the write voltage pulse V.sub.pp and channel potential Vch is smaller.
On the other hand, the specified transfer voltage pulse V.sub.pass is applied to the non-selection word line not to be written in, and the potential of the channel is raised to a certain potential from the initial potential by utilizing the capacitance between the gates and their channels. Therefore, as the transfer voltage pulse V.sub.pass is greater, the threshold fluctuation of the memory is smaller.
Thus, this transfer voltage pulse V.sub.pass is also applied to the memory cells in which "0" data is not written, among the memory cells connected to the selection bit lines provided with 0V for the bit lines BL1 to BLn. Therefore, the greater the transfer voltage pulse V.sub.pass, the less likely the threshold fluctuates. Considering these points, the minimum value and maximum value of the transfer voltage pulse V.sub.pass are determined.
Usually, this transfer voltage pulse V.sub.pass and write voltage pulse V.sub.pp are controlled by the "step-up system" for optimizing the specified initial voltage, the step voltage, the final voltage and the pulse width in order to narrow the distribution of the threshold for "0" data memory cells and to reduce writing errors.
To erase data, on the other hand, either "batch erase" for simultaneously erasing all memory cells in the NAND type cell, or "block erase" for erasing the cells in a specified by unit is selected. That is, in all or selected blocks, 0V is applied to all control gates, and in the case of block erase, a write voltage pulse V.sub.pp (for example, 20V) is applied to the control gate and selection gate of the non-selected blocks, and the bit line and source line are set in a floating state and a high voltage, for example, 20V is applied to the p-well. As a result, in all memory cells of all or selected blocks, electrons of the floating gate are released to the p-well, and the threshold moves in the negative direction. Furthermore, to read out data, a write voltage (for example, 4.5V) is applied to the selection gate transistors and word lines of non-selection memory cells other than the selection memory cells to turn them on, while 0V is applied to the word lines of the selection memory cells. At this time, by detecting the current flowing in the bit lines BL1 to BLn, either "0" or "1" data is judged.
However, in the "self-boost writing method" conventionally used for the NAND cell type EEPROM, the following problems were known, and have required solution.
FIG. 20 is a diagram showing an equivalent circuit of a NAND cell type EEPROM including electrodes of memory cells in floating channel writing, and memory cell A and memory cell B. Memory cell A is a write non-selection memory cell, having a floating channel, and provided with write voltage pulse V.sub.pp in the word line, in which "1" data is written. The memory cell B is a non-write, non-selection memory cell provided with 0V in the bit line and transfer voltage pulse V.sub.pass in the word line. Here, VBL is a voltage applied to the bit line, VSG is a voltage applied to the word line, and VSL is a voltage applied to the source line. In this example, the second memory cell counting from the bit lines BL1 to BLn is the selection word line, but an arbitrary memory cell is selected in usual operation.
Referring now to the timing chart in FIG. 21, the voltages on the electrodes corresponding to FIG. 20 and their timing are specifically described below.
First, for the bit lines BL1 to BLn, 0V or V.sub.CC (for example, 3.3V) is applied for the data to be written in; V.sub.CC (for example, 3.3V) is supplied to the selection gate SG1 side of bit lines BL1 to BLn and 0V is supplied to the selection gate SG2 of the source line SL side. In this state, the channel of the NAND cell of the bit line (BBL1) to write "1" data in is set in a floating state after the channel potential Vchinit is transferred. Afterwards, a write voltage pulse V.sub.pp is applied to the selection word line, and a transfer voltage pulse V.sub.pass is supplied to the non-selection word line, so that the channel in the floating state is boosted to the specified potential Vch. At this time, the relation between the channel potential Vch and the potential of each electrode is expressed by formula (1). EQU Vch=Vsg-V.sub.sgth (Vchinit)+Cr1(V.sub.pass-V.sub.passth -Vchinit)+Cr2(V.sub.pp -V.sub.passth -Vchinit)-(Tpw/16(Cins+Cch)).multidot.I (1)
In this formula (1), V.sub.sgth (Vchinit) denotes the threshold of the drain side selection gate at the channel potential of Vchinit, Cr1 indicates the channel boost ratio (the ratio of capacity of memory cell provided with transfer voltage pulse V.sub.pass to capacity depletion layer widening beneath the channel due to this pulse V.sub.pass), Cr2 is the channel boost ratio (the ratio of capacity of memory cell provided with a write voltage pulse V.sub.pp to a capacity of depletion layer widening beneath the channel due to this pulse V.sub.pp), and V.sub.passth shows the potential necessary for turning on the memory cell provided with transfer voltage pulse V.sub.pass when the channel potential is Vchinit. Tpw is the write voltage pulse width, Cins is the capacity per memory cell, Cch is the depletion layer widening beneath the channel, and I shows the current flowing from the channel through the well or adjacent bit line.
Depending on the profile of impurity concentration (boron impurity concentration, etc., when forming in p-wells) in the selection gate SG1, SG2, memory cells, and the semiconductor substrate in which they are formed, impurity concentration of channel implant injected into channels of selection gates SG1, SG2 and memory cells, and various conditions for forming the selection gates and memory cells, the initial voltage Vchinit to be transferred from the bit lines BL1 to BLn to the channel may be lowered. Alternately, the channel boost efficiency (Cr1, Cr2) may be lowered due to the increase in the capacity of the depletion layer beneath the channel or between the 0V terminal and channel, and therefore sufficient channel potential may not be obtained. Consequently, the threshold of the memory cell of "1" data writing may fluctuate, and writing errors may occur.
FIG. 22 is a diagram showing the relation of the transfer voltage pulse V.sub.pass in the above-described case of writing, and the threshold of the memory cell (memory cell A) for writing the "1" data. In the diagram, the axis of ordinates denotes the threshold, and the axis of abscissas indicated V.sub.pass, symbol A relates to the characteristic of cell A, and B shows the characteristics of cell B. As shown in the diagram, unless the transfer voltage pulse V.sub.pass is sufficiently large, the threshold of the memory cell A fluctuates to the positive side. By contrast, if the transfer voltage pulse V.sub.pass is too large, the threshold of the memory cell B fluctuates.
Such threshold fluctuations tend to be larger along with increases in the fluctuation of the writing characteristic due to non-uniformity of the gate width, gate length, wing width, tunnel oxide film thickness, inter-poly insulation film (inter-layer insulation film) thickness and other conditions of the memory cells. In particular it is more likely to occur as the number of bits of the selection block is larger when writing.
Moreover, if the leak current is large in the floating channel, in the source-drain diffusion layer, between wells, or between adjacent bit lines, the threshold fluctuation is much larger. Or, when transferring the bit line potential to the channel, characteristic fluctuations of the selection gate transistor may be further larger.
It is thus known that the characteristics of the memory cells and selection gate transistors impair the writing error characteristics, and for their improvement, it is required to improve the process, structure and operation (see D. J. Kim: "Process Integration for the high Speed NAND Flash Memory Cell" and "A Novel Booster Plate Technology in High Density NAND Flash Memories for Voltage Scaling-Down and Zero Program Disturbance" in 1996 Symposium on VLSI Technology Digest of Technical Papers, which gives rise to problems such as complication of process, increase in the number of processes, and increase of chip size. Besides, the presence of threshold fluctuation may have significant effects on data holding characteristics of memory cells when reading or letting stand, possibly leading to decline of reliability.
In the conventional approaches to reducing writing errors, nothing is mentioned about the timing of applying the write voltage pulse V.sub.pp or transfer voltage pulse V.sub.pass to the non-selection word line, or adjusting the rise time and fall time, and no measure has been put in practical use.
In particular, hitherto, concerning the write voltage pulse V.sub.pp and transfer voltage pulse V.sub.pass, it was believed that the writing errors could be minimized by applying the pulse V.sub.pp while boosting the channel potential by the pulse V.sub.pass. To the contrary, this further increases the writing errors.
FIGS. 23A and 23B are diagrams showing the timing of the conventional write voltage pulse V.sub.pp and transfer voltage pulse V.sub.pass. FIG. 23A shows V.sub.pp, and FIG. 23B shows V.sub.pass. In these diagrams, t1, t1' are the time to generate pulses V.sub.pp, V.sub.pass respectively, t2, t2.varies. are the time to reach the maximum value after the rise of the pulses, t3, t3' are the times to start falling, and t4, t4' are the times until the pulses fall completely. In the prior art, the pulses V.sub.pp and V.sub.pass are applied almost simultaneously. Alternately, in the belief that pulse V.sub.pass should be generated earlier than pulse V.sub.pp, pulse V.sub.pp is given later (t1.gtoreq.t1'), and hence the pulse V.sub.pass rise slightly earlier (t2'&lt;t2). Concerning the fall, either the pulses fall simultaneously or the pulse V.sub.pass falls later (t3.gtoreq.t3', t4&lt;t4') according to the belief that the pulse V.sub.pass should be present while pulse V.sub.pp is being generated. Actually, however, the pulse timing is not strictly controlled, and includes fluctuations, with all memory cells are not always operating at such timing. Hence, writing errors are more likely to occur.